A Combined 16-bit Binary and Dual Galois Field Multiplier
نویسندگان
چکیده
Galois field arithmetic is commonly used in Reed-Solomon encoding and decoding. This paper presents the design of a combined 16-bit binary and dual Galois field (GF) multiplier. This multiplier is capable of performing either a 16-bit two’s complement or unsigned multiplication, or two independent 8-bit GF(28) multiplications in SIMD fashion. The combined multiplier is designed by modifying a conventional binary tree multiplier. It uses a novel wiring methodology to provide two simultaneous GF(28) multiplies with a minor impact on area and delay. Three alternatives for the multiplier design are presented. Area and delay estimates indicate that compared to a conventional binary tree multiplier, the combined multiplier has roughly 6% more delay and 23% more area.
منابع مشابه
Hardware Implementation of Efficient Modified Karatsuba Multiplier Used in Elliptic Curves
The efficiency of the core Galois field arithmetic improves the performance of elliptic curve based public key cryptosystem implementation. This paper describes the design and implementation of a reconfigurable Galois field multiplier, which is implemented using field programmable gate arrays (FPGAs). The multiplier of Galois field based on Karatsuba’s divide and conquer algorithm allows for re...
متن کاملEfficient implementation of low time complexity and pipelined bit-parallel polynomial basis multiplier over binary finite fields
This paper presents two efficient implementations of fast and pipelined bit-parallel polynomial basis multipliers over GF (2m) by irreducible pentanomials and trinomials. The architecture of the first multiplier is based on a parallel and independent computation of powers of the polynomial variable. In the second structure only even powers of the polynomial variable are used. The par...
متن کاملFast Software Polynomial Multiplication on ARM Processors Using the NEON Engine
Efficient algorithms for binary field operations are required in several cryptographic operations such as digital signatures over binary elliptic curves and encryption. The main performance-critical operation in these fields is the multiplication, since most processors do not support instructions to carry out a polynomial multiplication. In this paper we describe a novel software multiplier for...
متن کاملDesign and Implementation of MOSFET Circuits and CNTFET, Ternary Multiplier in the Field of Galois
Due to the high density and the low consumption power in the digital integrated circuits, mostly technology of CMOS is used. During the past times, the Metal oxide silicon field effect transistors (MOSFET) had been used for the design and implementation of the digital integrated circuits because they are compact and also they have the less consumption power and delay to the other transistors. B...
متن کاملA High Speed, Optimized Multiplier Architecture for a DF-ECC Processor
This paper presents a High speed, optimized multiplier architecture for a dual-field (DF) processor for elliptic curve cryptography (ECC). This processor can support the required operations in both galois prime field GF(p) and binary field GF(2). The performance of the processor is enhanced by the judicious selection of proper type of coordinates in the arithmetic unit. The arithmetic unit is d...
متن کامل